• Automotive SW and Embedded Systems
• Systems Engineering
• Customer RFQ?s and Management of Project Acquisition Phases
• Software and Systems Architecture; iSAQB® - UML and SysML
• ASPICE Process Compliance Guidance and Trainings
• Requirements Engineering
• AUTOSAR
• Functional Safety with ISO 26262
• RTOS Real-Time Operating Systems Design and OSEK Expertise
• Automotive Cybersecurity with ISO 21434
• iSAQB Preparation and Certification Methodology
• Technical Management and Team Leadership
• Broad Automotive OEMs and Tier1 Experience

Automotive System Architect ? Technical Architect of BOSE Qualcomm Partnership:

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Technical responsibility and management of OEM RFIs and RFQs: GM, Renault.

• Early discussions with OEMs, Partners, Contractors, and 3rd-Parties, to allow the best technical agreements for BOSE Automotive.
• Developing a common system & software architecture among different OEMs using EA and Systems/SW modelling tools.
• Experience with Qualcomm Snapdragon Automotive SoCs and SW ecosystems; SA8255, SA8295, SA7255, SA6155.
• Technical management and coordination of Systems Engineers for Common Platform Team.
• Responsibility for ASPICE compliance and delivery of Systems Engineering work products.
• Defining Systems Engineering development process, and Systems Integration and Validation Test Strategy.
• Technical management and Acting Partner Manager for BOSE Automotive Division, representing BOSE in the official communication channels with Qualcomm.
• Preparation and participation of QBR/QTR Quarterly Business Review/Quarterly Technical Review between BOSE and Qualcomm.

Perfectly Keyless ECU ? GM / FCA / BaseKit Standard Platform

• Early setup of discussions and brainstorming for project activities and milestones planning with Project Leads, communicated to upper management.
• Responsibility over process topics, ASPICE and Product Engineering workflows. Conducting trainings to the team for SWE1, SWE2, and SWE3 processes.
• Daily communication with the development team and contribution to the project SW Architecture & SW Design repositories using IBM Rhapsody design tool.
• Designing memory protection concept for product security and functional safety with the controller memory protection unit (MPU).
• Responsibility over Operating System activities, Functional Safety, Runtime Measurements set-up, multi-Core setup.
• Design of SW dynamic behavior and SW scheduling scheme.
• Performing peer reviews on other activities within the team.
• Developer support for setting up BSW Vector OS, activation of Slave Core, MPU, and CPU Load utilization.
• Overall architecture responsibility over the AUTOSAR BSW on ST PowerPC chip, within a multi-CPU ECU.
• Active participation of pre-production FMEA & FTA activities for SW functional safety.
• With the collaboration of the whole team, helped assure successful technical deliveries as per planned milestones.

• Contributing to achieving Automotive Safety Integrity Level compliance for the project, among a highly professional team from BOSCH and VW.
• Responsibility over MCU Memory Protection context switching between ASIL and non-ASIL SW components.
• Reviewing ECU startup phases to assure Functional Safety compliance.
• Monitoring dynamic runtime behavior and CPU Load, affected by MPU switching overhead.
• Performing peer reviews with members of the development team.
• Handling communication with different SW teams to achieve ASIL compliance.
• Participant in daily standup and technical meetings for Functional Safety tracking.
• Monitoring, planning, and reporting SW safety status to the department management.
• Responsibility over optimizing CPU Load and balancing SW behavior on multi-core environment.
• Weekly reporting to VW & Luxoft for SW dynamic behavior.

• Responsibility over the runtime analysis and simulation of SW dynamic behavior.
• Responsibility over project CPU load measurements.
• Representing BOSCH in technical communication and agreements with INCHRON.
• Monitoring a student working as an intern in BOSCH in runtime analysis and simulation topic.
• Monitoring, planning, and reporting SW runtime status to the department management.
• Handling communication with VW, iSystem, and INCHRON for runtime analysis topic.
• Attending weekly technical meetings with VW Software Analyst.

3 months

Role: Senior Embedded Software Engineer / Tech Lead

Customer: BMW

Tasks:

iCAM3 RFK Camera System 

• Responsibility over the overall SW architecture and design.
• Training and technical guidance for 2 junior engineers in their ramp-up phase.
• Analysis and discussions of BMW requirements with system engineers to commit on SW responsibility.
• Review of the initial SW SRS requirements written by the team.
• Monitoring, planning, reporting to Valeo BMW operations manager.

1,3 Years

Role: Senior Embedded Software Engineer

Customer: BAIC

Tasks:

Surrounding View Camera System 

• Designed and implemented BLE (Bootloader Extension) to communicate with TI VisionMid A8 core for flashing slave DSP through SPI lines. BLE is being used in production line to flash the ECUs out for customer. This activity included:
  • Reverse engineering and code tracing of legacy black box Bootloader, to identify the required interface points between BL which handles CAN, and BLE which handles SPI.
  • Designing a generic BLE for slave core flashing.
  • Implementing a retry mechanism for failed SPI data chunks.
  • Implementing a CRC verification mechanism to ensure successful flashing on slave core side.
  • Writing generic, re-usable clean code for BLE SW Module, complying with MISRA C rules, ensured by PC-Lint static analysis tool.
  • Debugging through low level MCU peripherals; Flash Memory Module, SPI Module, CPU Clock Oscillator.
  • The newly used BLE contributed significantly to minimizing project costs for COTS (Components-Off-The-Shelf).
• Handled full communication and technical agreements with the Bootloader supplier as below:
  • Presented the Application team and have been the interface point between the two teams.
  • Provided design for shared memory area between BL and Application.
  • Led the agreements with BL supplier regarding the diagnostics transition techniques between the two SW parts.
  • Full ownership over external watchdog refreshment mechanism and dynamic handling between BL and Application.
  • Bug reporting, tracking and on-site support.
• Designed and implemented an in-house Scheduler Manager BSW Package. The Scheduler Manager was developed to save costs and replace an existing commercial Operating System. This activity included:
  • Reverse engineering and tracing through an existing AUTOSAR OS to understand the OS behavior, and replace such behavior with the new SchM package.
  • Removal of OS from the SW through the AUTOSAR configuration tool.
  • De-coupling SW modules and tasks from the OS.
  • Removal of the OS from the SW build system.
  • Designing and implementation of MCU start-up code in Assembly.
  • Designing and implementation of system Linker Script, and ROM/RAM distribution between SW modules.
  • Handling system stack memory area.
  • Implementation of MCU Core Exception Table, and Interrupt Vector Table.
  • Writing low level HW drivers for the below peripherals:
    • MCU Interrupt Controller.
    • MCU STM Timer, with 5 ms tick time.
  • Designing, implementing, and maintaining a non-preemptive Scheduler Manager to drive the SW modules, with strict compliance to the following specifications:
    • Rate-Monotonic Scheduling technique.
    • Very light scheduling processing overhead.
    • Small ROM and RAM memory footprint.
    • Simple 3-state automata state machine.
    • Generic clean coding for re-usability.
    • ?MISRA C compliance through PC-Lint Tool.
  • Supporting the integration testing team to spot any possible bug in the new SchM package.
  • Providing complete analysis and profiling of each system task execution time, deadline, periodicity and CPU load.
  • Balancing and re-distribution of system tasks to lower down overall CPU Load from originally 80% to finally reach 32%.
• Responsible for ASPICE pre-assessment of the project in the following areas:
  • SWE1: Software Requirements Analysis
  • SWE2: Software Architectural Design
  • SUP8: Configuration Management

• Presented the team in the pre-assessment meetings, along with the project leader and team leader.
• Debugging via Lauterbach Trace32 Debugger for PowerPC.
• Creation of High level design objects/requirements, specification of interaction sequences, component interfaces, state machines, and UML dynamic behavior diagrams using Enterprise Architect.
• Reviewing System Requirements related to SW scope written by System Engineers via IBM Doors.
• Analysis of Hardware to Software Interface document, and creation of related High Level Design Objects/Requirement to ensure traceability.
• Participating in bi-weekly Sprint Planning meetings along with SW project leader, software teams in India, Ireland and China to discuss effort estimations and assignation per team for each upcoming sprint.
• Responsible for technical coaching and code reviews of India Team, consisting of 3 SW engineers.
• Providing pre-commit code reviews for both India and Egypt teams, to ensure code quality as per internal development guidelines, ensure updates of SW Requirements, and High-Level Design Requirements to comply with Commit Control Board process.
• Conducting technical training for China team in Cairo site, consisting of 2 SW Engineers.

6 months

Role: Embedded Software Engineer

Customer: R&D

Tasks:

Low-Cost Software Platform Project

• Reverse engineering of legacy Volvo PAC360 Surrounding View System. Legacy tools have been used as references for designing the new platform.
• Design, implementation of DSP Handler SW module (DSPH), lying on top of stack of SPI, IPC layers. DSPH has been used as a generic way to interface MCUs with DSP cores.
• Run PC-Lint static analysis tool for DSPH module and ensure compatibility with MISRA-C guidelines.
• Providing full documentation, design and requirements specifications for the DSPH module via IBM DOORS.
• Designing the modules internals using Enterprise Architect.
• Attending technical meetings and workshops to interface with other module owners.
• Noticeable contribution to the final form of the platform.

1,5 Years

Role: Junior Embedded Software Engineer

Customer: Jaguar Land Rover 

Tasks:

Rear View Camera System 

• Full design and implementation of HMI Touch Screen driver. The driver allowed the ECU to communicate with the vehicle touch screen via CAN.
• Design and implementation of VDC (Video Display Control) SW module.
• Full implementation of AppM module (Application Manager), a centralized point to drive SW modules lying in the Application Layer.
• Bug fixing and debugging using Microchip In-Circuit Debugger for dsPIC microcontrollers.
• Performance measurements, release tests, and integration testing on project horizontal scope; diagnostics, and view switching, using Agilent Oscilloscopes.
• Participation in daily 5-minutes meetings, bi-weekly sprint planning inter-call meetings, and Daily Commit Reviews with Ireland team.
• Ownership and maintenance of Software Requirements Specification and High Level Design documents on DOORS.
• Highest number of commits into the project repository.
• Achieved ASPICE Level 2 with the team.